The present invention relates to a ferroelectric memory and a method of driving the same.
In recent years, a ferroelectric memory (ferroelectric random access memory (FeRAM)) using a ferroelectric capacitor as an information storage capacitor has attracted attention. The ferroelectric memory has been widely used as a memory provided to a transponder of a radio frequency identification (RFID) system.
Japanese Patent Application Laid-Open No. 2001-283583 discloses a technology for realizing a circuit which drives a wordline and a plateline of the ferroelectric memory. However, the FeRAM (ferroelectric memory) has many specific problems which do occur in an SRAM or the like.
An example is a problem relating to a plateline (PL) driver circuit. In the FeRAM, the PL driver circuit is necessary in addition to a wordline (WL) driver circuit, differing from the SRAM.
As the WL driver circuit for the FeRAM, a circuit similar to a WL driver circuit for the SRAM may be used. In the case where the gate load (load due to the parasitic capacitance of the gate connected with the wordline) of a transfer transistor which makes up a memory cell of the FeRAM is smaller than that of the SRAM, a WL driver circuit having a drive capability lower than that of the WL driver circuit used for the SRAM may be used.
The capacitive load of the ferroelectric capacitor included in each of the FeRAM memory cells disposed along the plateline is very large, and many ferroelectric capacitors are disposed along the plateline. Therefore, the PL driver circuit may need to drive a capacitive load as large as about one picofarad (pF). In order to drive such a large load, a circuit having a drive capability higher than that of the WL driver circuit is inevitably required as the PL driver circuit used for the FeRAM. This results in an increase in the chip area.
As a signal for controlling the PL driver circuit, a decode signal used for the WL driver circuit or a WL signal which is an output signal of the WL driver circuit may be used. However, the following problem occurs when using the decode signal. Specifically, since a circuit similar to a control circuit used for the WL driver circuit is also necessary for the PL driver circuit, the circuit area is inevitably increased, whereby chip cost is increased due to an increase in chip size.
On the other hand, the following problem occurs when using the WL signal. Specifically, when using a poly-interconnect as the WL interconnect, since the PL signal cannot be generated until the WL signal rises sufficiently, it is difficult to deal with high-speed memory access. In this case, the poly-interconnect for the WL signal may be backed with an aluminum interconnect in order to increase the speed of the WL signal. However, since this method requires the aluminum backing interconnect, process cost is increased.
Moreover, since the WL driver circuit and the PL driver circuit used for the FeRAM cannot be disposed along the direction of the short side of the memory cell due to the large circuit area, the WL driver circuit and the PL driver circuit are generally disposed along the direction of the long side of the memory cell. In the case where the arrangement area of the WL driver circuit and the PL driver circuit is large and does not conform to the pitch of the memory cells in the long side direction, it is necessary to increase the size of the memory cell in the long side direction corresponding to the WL driver circuit and the PL driver circuit, or dispose the WL driver circuit on the left of the memory cell array and dispose the PL driver circuit on the right of the memory cell array. However, since the above measures increase the chip area, chip cost is further increased.
Another example is a problem relating to a write failure of a logical “1” due to the effect of the threshold voltage of the transfer transistor which makes up the memory cell.
As shown in FIG. 1A described later, the memory cell of the FeRAM includes an N-type (NMOS) transfer transistor TR and a ferroelectric capacitor CS. One end of the transfer transistor TR is connected with the bitline BL, and the other end of the transfer transistor TR is connected with one end of the ferroelectric capacitor CS. A gate of the transfer transistor TR is connected with the wordline WL. The other end of the ferroelectric capacitor CS is connected with the plateline PL.
A problem relating to the write failure of the logical “1” when setting a wordline select voltage at a voltage VCC is described below.
Consider the case of writing a logical “0” into the ferroelectric capacitor CS (the case of applying 0 V to the bitline BL and applying the voltage VCC to the plateline PL). In this case, the voltage of the other end (PL side) of the ferroelectric capacitor CS is set at the voltage VCC, and the voltage (0 V) of the bitline BL is applied to one end (node NC side) of the ferroelectric capacitor through the transfer transistor TR. As a result, a voltage +VCC with respect to the bitline BL is applied to the ferroelectric capacitor CS. Consider the case of writing the logical “1” into the ferroelectric capacitor CS (the case of applying the voltage VCC to the bitline BL and applying 0 V to the plateline PL). In this case, the other end (PL side) of the ferroelectric capacitor CS is set at 0 V, and the voltage of the bitline BL charged to the voltage VCC is applied to one end (NC side) of the ferroelectric capacitor CS through the transfer transistor TR. Therefore, the voltage which has dropped to “VCC−VTH” due to the effect of the threshold voltage VTH of the transfer transistor TR is applied to one end (NC side) of the ferroelectric capacitor CS. As a result, the logical “1” is insufficiently written into the ferroelectric capacitor CS. This causes a problem in which data “1” cannot be read, or it is difficult to write data “1” since the ferroelectric capacitor CS is continuously imprinted in the data “0” state. This poses a serious problem when the threshold voltage (VTH) of the NMOS transistor (TR) is high and the power supply voltage (VCC) is low.
As described above, the FeRAM has a problem in which it is difficult to efficiently drive the wordline and the plateline using a small circuit configuration. It is an important technical subject to solve this problem.